EP3C40F484C6N vs EP3C40F484C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C40F484C6N sa pamamagitan ng Altera at EP3C40F484C8N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C40F484C6N | EP3C40F484C8N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone III | Cyclone III |
| Logic Elements (LE) | 39,600 | — |
| Total Memory Bits | 1,161,216 bits | — |
| Embedded 18x18 Multipliers | 396 | — |
| User I/O Pins (max) | 331 | — |
| PLLs | 4 | 4 |
| Process Technology | 65 nm low-k dielectric | TSMC 65 nm low-power CMOS |
| Core Voltage | 1.2 V | — |
| Packhaging | 484-FBGA (F484, 23x23 mm, 1.0 mm pitch) | 484-FBGA (23×23 mm, 1.0 mm pitch) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Speed Grade | C6 (commercial, -40C to +125C operating) | 8 (commercial) |
| Temperature na Operasyon | -40C to +125C | -40C to +85C (industrial) |
| Configuration Modes | JTAG, AS, AP, PS | AS, AP, PS, JTAG |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | — |
| Tindminan RoHS | Compliant (lead-free) | Lead-free / RoHS compliant |
| Logic Elements | — | 39,600 |
| Logic Array Blocks (LABs) | — | 2,475 |
| Embedded Memory | — | 1,161,216 bits (1134 Kbit M9K RAM) |
| Embedded 18×18 Multipliers | — | 126 |
| User I/Os | — | 331 |
| Global Clock Networks | — | 20 |
| Core Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| LVDS Data Rate | — | Up to 875 Mbps per pair |