EP3C5E144A7N vs EP3C5E144C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C5E144A7N sa pamamagitan ng Altera at EP3C5E144C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C5E144A7N | EP3C5E144C7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III | — |
| Logic Elements (LE) | 5,136 | 5,136 |
| Total Memory Bits | 423,936 bits (414 Kbits) | 423,936 |
| Embedded Memory Blocks | 46 x M9K (9 Kbit each) | — |
| Embedded 18x18 Multipliers | 23 | 46 |
| User I/O Pins | 94 | — |
| Number of I/O Banks | 4 | — |
| Number of PLLs | 4 | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Bank Voltage (VCCIO) | Per-bank, supports 1.2 V to 3.3 V | — |
| Packhaging | 144-LQFP Exposed Pad (EQFP, 22x22 mm) | 144-LQFP Exposed Pad (EQFP-144), 22x22 mm, 0.5 mm pitch |
| Speed Grade | 7 | C7 (7 ns delay) |
| Temperature Grade | Commercial (0C to +85C junction) | — |
| Process Technology | 65 nm low-k dielectric | TSMC 65 nm low-power |
| Configuration Modes | AS, PS, JTAG, Fast Passive Parallel | AS, PS, FPP, JTAG |
| Design Toolchain | Quartus II / Quartus Prime | — |
| Supported I/O Standards | LVDS, SSTL, LVTTL, PCI, LVCMOS | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Compliant (per DigiKey product page) | Compliant |
| Device Family | — | Cyclone III |
| Logic Array Blocks (LAB) | — | 290 |
| Embedded M9K Memory Blocks | — | 46 |
| PLLs | — | 4 |
| User I/Os | — | 94 |
| Temperature ng Junction na Operasyon | — | 0C to +85C |
| I/O Standards | — | LVDS, SSTL, HSTL, LVCMOS, PCI/PCI-X |