EP3C80U484C7 vs EP3C80U484C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3C80U484C7 sa pamamagitan ng Intel at EP3C80U484C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3C80U484C7 | EP3C80U484C7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | Cyclone III | — |
| Family | EP3C80 | — |
| Logic Elements | 81,264 | — |
| Embedded Memory | 2,810,880 bits (295 M9K blocks) | 2,810,880 bits |
| Embedded 18x18 Multipliers | 244 | — |
| PLLs | 4 | — |
| Maximum User I/O Pins | 429 (approximate, package-dependent) | — |
| Packhaging | 484-FBGA (UBGA) | — |
| Speed Grade | -7 (commercial) | — |
| Core Voltage | 1.2 V | — |
| I/O Voltage Range | 1.2 V to 3.3 V | — |
| Process Technology | 65 nm low-power CMOS | 65 nm |
| Temperature ng Junction na Operasyon | 0 C to 85 C (commercial) | — |
| Configuration Modes | Passive Serial, Active Serial, JTAG, AES-encrypted bitstream | — |
| Memory Interface Support | DDR, DDR2, QDRII SDRAM | — |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Product Family | — | Cyclone III |
| Logic Cell Count | — | 81,264 cells |
| User I/O Count | — | 295 I/O |
| Maksimum na Taktiko ng Oras | — | 437.5 MHz |
| Volte ng Pagbibigay | — | 1.2 V |
| Terminal Count | — | 484 terminals |
| Package Code | — | FBGA |
| Package Description | — | 484-UBGA |
| Package Shape | — | Rectangular |
| Terminal Form | — | Ball |
| Temperature Grading | — | Other |
| Style ng Pagpapasok | — | Surface Mount |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |