EP3CLS70U484I7 vs EP3CLS70U484C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3CLS70U484I7 sa pamamagitan ng Altera at EP3CLS70U484C8N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3CLS70U484I7 | EP3CLS70U484C8N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | Cyclone III LS | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 70,208 | — |
| Number of Logic Blocks | 4,612 | — |
| Total Memory Bits | 3,068,928 (3 Mb) | — |
| Number of M9K Memory Blocks | 247 | — |
| Number of Embedded 18x18 Multipliers | 247 | — |
| Number of PLLs | 4 | — |
| User I/O Pins | 278 | — |
| Package Type | 484-FBGA / 484-UBGA (UBGA-484) | — |
| Package Size | 19 mm x 19 mm | — |
| Ball Pitch | 1.0 mm | — |
| Core Supply Voltage | 1.2 V | 1.2 V |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.0 V / 3.3 V | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | 0C to +85C (commercial) |
| Process Technology | 60 nm low-power CMOS | TSMC 65 nm Low-Power (LP) |
| Configuration Modes | JTAG, Passive Serial, Active Serial, Fast Passive Parallel | AS, PS, JTAG, FPP |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | 3 (168 hours) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Family | — | Cyclone III LS |
| Logic Elements (LE) | — | 70,208 |
| Memory Bits | — | 3,068,928 bits |
| Maximum User I/O | — | 278 |
| DSP Blocks (18x18 Multipliers) | — | 247 |
| PLLs | — | 8 |
| Global Clock Networks | — | 20 |
| Speed Grade | — | 8 (commercial) |
| Packhaging | — | 484-FBGA (U484) FineLine BGA, 19x19 mm |