EP3SL340F1760C2 vs EP3SL340F1760C4 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL340F1760C2 sa pamamagitan ng Intel at EP3SL340F1760C4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP3SL340F1760C2 EP3SL340F1760C4
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Huling Pagbili
Series Stratix III L Stratix III L
Family Stratix III —
Logic Elements (LE) 337,500 —
Logic Array Blocks (LABs) 13,500 —
Embedded Memory (bits) 18,822,144 —
User I/O Count 1,120 1,120
DSP Blocks [DATA_NEEDED: DSP block count] [DATA_NEEDED: DSP block count]
Transceivers [DATA_NEEDED: transceiver count and max data rate] [DATA_NEEDED: number of embedded transceiver channels]
Maximum User I/O Voltage 3.3 V (LVTTL/LVCMOS supporting up to 3.0 V LVDS) —
Core Voltage 0.9 V / 1.1 V 1.1 V
Process Node 40 nm TSMC 65 nm
Packhaging 1760-ball FCBGA (FineLine BGA) 1760-BBGA, FCBGA (Flip-Chip)
Ball Pitch 1.0 mm —
Temperature na Operasyon 0C to +85C (Commercial, C2 suffix) 0C to +85C (commercial)
Tindminan RoHS Compliant Compliant
Configuration SRAM-based, supports JTAG, FPP, AS, PS —
Programmable Power Technology Yes —
PCIe Hard IP Yes (Gen1/Gen2) —
Logic Elements — 337,500
Embedded Memory Bits — 18,821,144
Maximum Core Frequency — 450 MHz
Speed Grade — C4 (commercial)
I/O Standards Supported — LVDS, LVTTL, LVCMOS, HSTL, SSTL, PCI, PCI-X
PLLs — [DATA_NEEDED: PLL count]
Configuration Scheme — Passive serial, fast passive parallel, JTAG
Lead-Free — Yes
Uri ng Pagpapasok — Surface Mount (BGA)

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