EP3SL340F1760C2 vs EP3SL340F1760I3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL340F1760C2 sa pamamagitan ng Intel at EP3SL340F1760I3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL340F1760C2 | EP3SL340F1760I3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Series | Stratix III L | — |
| Family | Stratix III | Stratix III L |
| Logic Elements (LE) | 337,500 | — |
| Logic Array Blocks (LABs) | 13,500 | 13,500 |
| Embedded Memory (bits) | 18,822,144 | — |
| User I/O Count | 1,120 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Transceivers | [DATA_NEEDED: transceiver count and max data rate] | — |
| Maximum User I/O Voltage | 3.3 V (LVTTL/LVCMOS supporting up to 3.0 V LVDS) | — |
| Core Voltage | 0.9 V / 1.1 V | 1.1 V |
| Process Node | 40 nm TSMC | — |
| Packhaging | 1760-ball FCBGA (FineLine BGA) | 1760-ball FC-FBGA (Flip-Chip BGA) |
| Ball Pitch | 1.0 mm | 1.0 mm |
| Temperature na Operasyon | 0C to +85C (Commercial, C2 suffix) | -40C to +100C (Industrial) |
| Tindminan RoHS | Compliant | Compliant |
| Configuration | SRAM-based, supports JTAG, FPP, AS, PS | — |
| Programmable Power Technology | Yes | — |
| PCIe Hard IP | Yes (Gen1/Gen2) | — |
| Logic Elements | — | 337,500 |
| Embedded Memory Bits | — | 18,821,144 bits |
| Maximum User I/O | — | 1120 |
| Process Technology | — | 65 nm CMOS |
| Speed Grade | — | I3 |
| Configuration Method | — | JTAG / Serial / Parallel |
| Lead-Free | — | Yes |
| Design Software | — | Quartus II (legacy) |