EP3SL340F1760I3 vs EP3SL340F1760C2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL340F1760I3 sa pamamagitan ng Intel at EP3SL340F1760C2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SL340F1760I3 - Stratix III L FPGA, 337.5K LE, 1760-BGA | Intel
EP3SL340F1760I3 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP3SL340F1760I3 | EP3SL340F1760C2 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Series | Stratix III L | Stratix III L |
| Logic Elements | 337,500 LE | — |
| LABs (Logic Array Blocks) | 13,500 | — |
| Embedded Memory Bits | 18,822,144 bit | — |
| User I/Os | 1120 | — |
| Number of Pins / Balls | 1760 | — |
| Package Type | FC-FBGA (1760-ball, FineLine BGA) | — |
| Package Code | BGA1760, 42x42, 40 | — |
| Core Voltage | 1.1 V | 0.9 V / 1.1 V |
| Process Technology | 65 nm | — |
| Temperature na Operasyon | -40 °C to 100 °C (Industrial grade, I3 suffix) | 0C to +85C (Commercial, C2 suffix) |
| Speed Grade | I3 (Industrial, mid-speed bin) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Compliant (Pb-free BGA balls) | Compliant |
| Configuration Memory | SRAM-based, volatile (requires external configuration device) | — |
| Transceivers | [DATA_NEEDED: transceiver count and data rate for this F1760 variant] | [DATA_NEEDED: transceiver count and max data rate] |
| DSP Blocks | [DATA_NEEDED: 18x18 multiplier count] | [DATA_NEEDED: DSP block count] |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Level ng MSL | MSL3 (JEDEC J-STD-020, reflow 245 °C peak) | — |
| Family | — | Stratix III |
| Logic Elements (LE) | — | 337,500 |
| Logic Array Blocks (LABs) | — | 13,500 |
| Embedded Memory (bits) | — | 18,822,144 |
| User I/O Count | — | 1,120 |
| Maximum User I/O Voltage | — | 3.3 V (LVTTL/LVCMOS supporting up to 3.0 V LVDS) |
| Process Node | — | 40 nm TSMC |
| Packhaging | — | 1760-ball FCBGA (FineLine BGA) |
| Ball Pitch | — | 1.0 mm |
| Configuration | — | SRAM-based, supports JTAG, FPP, AS, PS |
| Programmable Power Technology | — | Yes |
| PCIe Hard IP | — | Yes (Gen1/Gen2) |