EP3SL50F780C3 vs EP3SL50F780C4G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL50F780C3 sa pamamagitan ng Intel at EP3SL50F780C4G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SL50F780C3 - Stratix III L FPGA, 47.5K LE, 780-FBGA | Intel / Altera
EP3SL50F780C3 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP3SL50F780C3 | EP3SL50F780C4G |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | Stratix III L (low-power) | Stratix III L |
| Series | Stratix III | EP3SL50 |
| Logic Elements | 47,500 | 47,500 |
| Logic Array Blocks (LABs) | 1,900 | — |
| Embedded Memory Bits | 2,184,192 | 2,184,192 |
| User I/Os | 488 | — |
| Package Type | 780-BBGA, FCBGA (FineLine) | — |
| Device Pin Count | 780 | — |
| Temperature na Operasyon | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
| Speed Grade | 3 | 4 |
| Supply Voltage (Core) | [DATA_NEEDED: VCCINT nominal value] | — |
| PLLs | 12 | 4 |
| Global Clock Networks | 24 | — |
| Process Node | 65 nm TSMC | — |
| Configuration Method | SRAM-based, supports Partial Reconfiguration | FPP / FAS / JTAG |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free / Halogen-Free | Lead-Free (per package marking); Halogen-Free status unknown | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | MSL3 (per JEDEC J-STD-020, typical for large FBGA) | — |
| Maximum User I/Os | — | 488 |
| Process Technology | — | 65 nm |
| Core Voltage (VCC) | — | 1.1 V |
| Packhaging | — | 780-ball FC-FBGA |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead-Free | — | Yes |