EP610DC-20 vs EP610DC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-20 sa pamamagitan ng Intel at EP610DC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-20 | EP610DC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Classic EP610 | EP610 (Classic Device Family) |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | 16 |
| I/O Pins | 16 (bidirectional) | 16 (with output enable) |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 30 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | Commercial (0C to +70C) |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CERDIP (windowed) |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| Uri ng Pagpapasok | Through-hole | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Macrocells | — | 16 |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |