EP610DC-20 vs EP610DC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-20 sa pamamagitan ng Intel at EP610DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-20 | EP610DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | Altera Classic EP610 |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 (bidirectional) | — |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 35 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Temperature na Operasyon | 0 °C to 70 °C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Packhaging | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | CMOS |
| Uri ng Pagpapasok | Through-hole | Through-Hole (DIP) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |