EP610IDC-10 vs EP610ILC10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610IDC-10 sa pamamagitan ng Intel at EP610ILC10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610IDC-10 | EP610ILC10 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS, UV-erasable / OTP |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 20 | — |
| Hanay ng Temperature na Operasyon | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status of CDIP-10 variant] | Unknown - verify with manufacturer |
| Uri ng Pagpapasok | Through-hole | Surface Mount / Socket |
| Family | — | Classic EPLD (EP610) |
| Logic Elements | — | 16 macrocells |
| Gates | — | 300 gates equivalent |
| Product Terms | — | 160 |
| I/O Lines | — | 16 |
| Propagation Delay (tPD) | — | 15 ns (10 ns speed grade) |
| Maximum Internal Frequency | — | 100 MHz |
| Temperature na Operasyon | — | -40 C to +85 C (Industrial) |
| Architecture | — | PAL-type AND-OR-NOT |
| Packhaging | — | 28-pin PLCC (J-Lead) |