EP610ILC10 vs EP610ILC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC10 sa pamamagitan ng Intel at EP610ILC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610ILC10 | EP610ILC-25 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD (EP610) | Classic EPLD (EP610 series) |
| Logic Elements | 16 macrocells | — |
| Gates | 300 gates equivalent | — |
| Product Terms | 160 | 160 |
| I/O Lines | 16 | — |
| Dedicated Inputs | 4 | 4 |
| Propagation Delay (tPD) | 15 ns (10 ns speed grade) | — |
| Maximum Internal Frequency | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Temperature na Operasyon | -40 C to +85 C (Industrial) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| Architecture | PAL-type AND-OR-NOT | — |
| Packhaging | 28-pin PLCC (J-Lead) | 28-pin PLCC (J-lead) |
| Uri ng Pagpapasok | Surface Mount / Socket | Surface Mount |
| Tindminan RoHS | Unknown - verify with manufacturer | [DATA_NEEDED: RoHS status] |
| Device Type | — | EEPLD (Electrically Erasable PLD) |
| Usable Gates | — | 300 |
| Macrocells | — | 16 |
| Maximum Operating Frequency (fMAX) | — | 40 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Nominal Supply Voltage | — | 5 V |
| Total Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Hanay ng Temperature na Operasyon | — | 0 C to +70 C (commercial) |
| Process Technology | — | CMOS, electrically erasable |
| Programming Method | — | In-system, electrically erasable |