EP610LC-25 vs EP610LC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-25 sa pamamagitan ng Intel at EP610LC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610LC-25 | EP610LC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | 100 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Volte ng Pagbibigay | 5 V ±5% | — |
| Technology | CMOS | CMOS EEPROM (one-time-programmable plastic) |
| Programmability | UV-erasable (windowed package) | — |
| Packhaging | PLCC-28 | 28-pin PLCC (J-lead) |
| Temperature na Operasyon | 0C to +70C (commercial) | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| I/O Pins | [DATA_NEEDED: exact I/O count] | — |
| Tindminan RoHS | [DATA_NEEDED] | [DATA_NEEDED: rohs_status] |
| Device Series | — | EP610 |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 37 ns |
| Supply Voltage (Vcc) | — | 5 V |
| Speed Grade | — | -35 (slowest EP610) |
| Programmable Pins | — | 24 input / 16 output (shared macrocells) |
| Lead-Free | — | [DATA_NEEDED: lead_free] |
| Level ng MSL | — | [DATA_NEEDED: msl_level] |
| Programming Tool | — | MAX+PLUS II development system |