EP610LC15 vs EP610LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC15 sa pamamagitan ng Rochester Electronics at EP610LC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15 Obsolete
Pagsanggunian na paghahambing
| Parametro | EP610LC15 | EP610LC-30 |
|---|---|---|
| Brand | Rochester Electronics | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP610) | — |
| Number of Macrocells | 16 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Toggle Frequency (fMAX) | 83.3 MHz | — |
| Supply Voltage (VCC) | 5 V (±10%) | 4.75 V to 5.25 V |
| Dedicated Inputs | 10 | — |
| I/O Pins | 16 | — |
| Total Logic Pins | 24 | — |
| Technology | UV-erasable EPROM, CMOS | CMOS EPROM (UV-erasable) |
| Packhaging | PLCC-28 (J-Lead) | 24-pin CERDIP / PDIP |
| Temperature na Operasyon | 0 °C to +70 °C (LC suffix = commercial) | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Programming Interface | Altera 4-pin serial (Classic algorithm) | — |
| Security Bit | Yes (programmable) | — |
| Tindminan RoHS | Compliant (Rochester re-creation) | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD (EP610) |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Pipelined Data Rate | — | up to 100 MHz |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| Uri ng Pagpapasok | — | Through-Hole |
| Type ng Output | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |