EP610LI-15 vs EP610DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LI-15 sa pamamagitan ng Altera at EP610DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP610LI-15 - 16-Macrocell CMOS EPLD, 15ns tPD | Altera (Rochester)
EP610LI-15 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP610LI-15 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Family | Classic EPLD EP610 | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 15 ns | 15 ns (speed grade -15) |
| Counter Frequency (fCNT) | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Temperature na Operasyon | 0 C to +70 C (commercial, "I" grade) | 0C to 70C (commercial) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| Packhaging | 24-pin ceramic DIP, side-brazed, windowed (DIP-24) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Bilang ng Pin | 24 | — |
| Programming Method | UV erase + EPROM programmer | JEDEC fuse map, UV erasure |
| Logic Blocks | AND/OR array, 16 output macrocells | — |
| I/O Standard | TTL/CMOS compatible | — |
| Type ng Output | 3-state | — |
| Tindminan RoHS | Non-compliant (ceramic DIP, SnPb finish typical) | [DATA_NEEDED: RoHS status] |
| Manufacturer (current) | Rochester Electronics (authorized Altera legacy distributor) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Product Family | — | Classic EPLD (EP610) |
| Architecture | — | UV-erasable CMOS PAL-type |
| Logic Expanders | — | 4 |
| Dedicated Inputs | — | 20 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Uri ng Pagpapasok | — | Through-Hole |
| Technology | — | CMOS |