EP610PC-25T vs EP610DC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-25T sa pamamagitan ng Intel at EP610DC-25 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Huling PagbiliRochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP610PC-25T | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | — |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Packhaging | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | 0 C to +70 C |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | JEDEC fuse-map / UV-erase |
| Uri ng Pagpapasok | Through-hole | Through Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Shipping Form (T suffix) | Tube | — |
| Family | — | Altera Classic EPLD |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | — | -25 (25 ns tPD) |