EP910ILC-12 vs EP910DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-12 sa pamamagitan ng Intel at EP910DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILC-12 | EP910DC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera EP910 Classic EPLD | Altera Classic EPLD |
| Number of Macrocells | 24 | — |
| Usable Gates | 450 (typical) | — |
| Propagation Delay (tPD) | 12 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (typical) |
| Nominal Supply | 5 V | — |
| Memory Technology | UV-erasable CMOS EPROM | — |
| Packhaging | 28-PLCC (J-Lead, 11.5 x 11.5 mm) | 24-pin ceramic DIP (DC) |
| Uri ng Pagpapasok | Surface Mount | Through-Hole |
| Temperature na Operasyon | -40 °C to +85 °C (industrial grade, 'I' suffix) | 0C to +70C (commercial) |
| Configuration Storage | Non-volatile EPROM (instant-on) | — |
| Programming Method | Altera programming algorithm (serial/parallel master-slave) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Bilang ng Pins | 28 | — |
| Feedback Paths | 16 dedicated | — |
| Device Density | — | 900 usable gates |
| Macrocells | — | 24 |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Technology | — | CMOS EPROM, UV-erasable |