EP910ILC-15 vs EP910LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-15 sa pamamagitan ng Intel at EP910LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILC-15 | EP910LI-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Classic EPLD | Altera Classic EPLD |
| Series | EP910 | — |
| Logic Gates | 450 | — |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 83.33 MHz | — |
| Volte ng Pagbibigay | 5 V | 5 V (4.75 V to 5.25 V) |
| Uri ng Memory | EPROM (UV-erasable) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40 °C to +85 °C (Industrial) |
| Packhaging | 44-pin PLCC (J-lead) | 44-pin PLCC (J-lead) |
| Uri ng Pagpapasok | Surface Mount (SMT) | Surface Mount |
| Propagation Class | -15 speed grade | — |
| Storage Condition | Dry cabinet, humidity-controlled | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |