EP910ILC-50 vs EP910LC-40H Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-50 sa pamamagitan ng Intel at EP910LC-40H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILC-50 | EP910LC-40H |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD (EP910) |
| Macrocells | 24 | — |
| Usable Gates | 900 (typical) | 450 |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 24 | — |
| Dedicated Input Pins | 12 | — |
| Packhaging | PLCC-44 (J-lead) | 40-pin Ceramic DIP (CDIP-40), JEDEC standard |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Through-Hole (THT) |
| Technology | CMOS EPROM, UV-erasable | CMOS, UV-erasable EPROM |
| Temperature na Operasyon | 0C to +70C (commercial) | -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] |
| Macro Cells | — | 24 |
| Logic Elements | — | 24 macro cells / expandable to 48 via expander terms |
| Propagation Delay (tPD) | — | 40 ns max |
| Supply Current (ICC) | — | Low-power CMOS, typical ICC < 100 mA |
| Speed Grade | — | -40 (40 ns tPD) |
| Programming Method | — | UV-erase + EPROM program, ~100 erase cycles |
| I/O Pins | — | [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] |