EP910ILI-25 vs EP910DC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILI-25 sa pamamagitan ng Altera at EP910DC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910ILI-25 | EP910DC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 36 |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | 30 ns (max) |
| Technology | CMOS, EPROM | — |
| Architecture | PAL-type with global interconnect bus | PAL-type AND-OR sum-of-products, CMOS |
| Packhaging | PLCC-44 (windowed ceramic, J-lead) | DIP-40 (through-hole, 600 mil) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | UV-Erasable / OTP |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| Tindminan RoHS | Non-compliant (windowed ceramic package) | — |
| Family | — | Classic EPLD (EP910 series) |
| Gate Count | — | 900 usable gates |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Volte ng Pagbibigay | — | 5 V |
| Process Technology | — | CMOS |
| Uri ng Pagpapasok | — | Through-Hole |