EP910IPC-12 vs EP910DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-12 sa pamamagitan ng Altera at EP910DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-12 | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| Dedicated Inputs | 10 | 12 |
| I/O Pins | 24 | — |
| Packhaging | 40-pin PDIP | 24-pin ceramic DIP (DC) |
| Uri ng Pagpapasok | Through Hole | Through-Hole |
| Technology | CMOS EPLD (UV-erasable or OTP) | CMOS EPROM, UV-erasable |
| Temperature na Operasyon | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly stated in verified data] |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |