EP910IPC-12 vs EP910ILC-12 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-12 sa pamamagitan ng Altera at EP910ILC-12 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-12 | EP910ILC-12 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Classic EPLD | Altera EP910 Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | 450 | 450 (typical) |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Dedicated Inputs | 10 | — |
| I/O Pins | 24 | — |
| Packhaging | 40-pin PDIP | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Uri ng Pagpapasok | Through Hole | Surface Mount |
| Technology | CMOS EPLD (UV-erasable or OTP) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 12 ns (max) |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| Programming Method | — | Altera programming algorithm (serial/parallel master-slave) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Bilang ng Pins | — | 28 |
| Feedback Paths | — | 16 dedicated |