EP910IPC-25 vs EP910ILI-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-25 sa pamamagitan ng Intel at EP910ILI-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-25 | EP910ILI-25 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | — |
| Manufacturer | Altera (now Intel) | — |
| Architecture | PAL-type EPLD, CMOS, UV/OTP | PAL-type with global interconnect bus |
| Usable Gates | 450 | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | 240 (maximum) |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Maximum Frequency (fMAX) | 40 MHz | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Lines | 24 | — |
| Total Inputs (max) | 36 | — |
| Total Outputs (max) | 24 | — |
| Supply Voltage (VCC) | 5 V | — |
| Temperature na Operasyon | 0C to +70C (commercial grade) | -40C to +85C (Industrial) |
| Packhaging | 40-pin PDIP (PDIP-40) | PLCC-44 (windowed ceramic, J-lead) |
| Uri ng Pagpapasok | Through-Hole | — |
| Programming Method | EPROM cell (OTP / UV erasable) | UV-erasable (windowed), MAX+PLUS II programmer |
| Development Tool | MAX+PLUS II | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | EP910 (Classic EPLD) |
| I/O Pins | — | 24 |
| Technology | — | CMOS, EPROM |
| Operating Voltage | — | 5 V (4.75 V to 5.25 V) |
| Logic Test Circuitry | — | On-board JTAG-compatible test |
| Tindminan RoHS | — | Non-compliant (windowed ceramic package) |