EP910LC-30 vs EP910LC-35T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-30 sa pamamagitan ng Altera at EP910LC-35T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-30 | EP910LC-35T |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocell Count | 24 | — |
| Propagation Delay (tPD) | 30 ns (max) | 35 ns |
| Maximum Toggle Frequency | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal, TTL) | 5 V |
| Process Technology | CMOS (EPROM-based) | CMOS (EPROM-based) |
| Package Type | PDIP-40 (Plastic DIP, through-hole) | — |
| Operating Temperature Grade | Commercial (0C to +70C) | — |
| I/O Pin Count | 24 | — |
| Dedicated Input Pins | 36 (including I/O) | — |
| Product Terms per Macrocell | Up to 16 | — |
| Programming Technology | UV-erasable EPROM cell | — |
| Development Tool | Altera MAX+PLUS II | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | MSL 3 (168 hours) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in verified data] |
| Family | — | Classic EPLD (EP910) |
| Logic Capacity | — | 450 usable gates |
| Macrocells | — | 24 |
| Maximum Operating Frequency | — | 28.6 MHz |
| User I/O Pins | — | 36 |
| Packhaging | — | PLCC-44 (J-lead) |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Erasure Method | — | UV-erasable window (ceramic package) / OTP (plastic) |
| Programming | — | Altera programming hardware + MAX+PLUS II |
| Uri ng Pagpapasok | — | Surface Mount (PLCC socket or solder) |