EP910LC44-40 vs EP910LC-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC44-40 sa pamamagitan ng Altera at EP910LC-40 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 ObsoletePagsanggunian na paghahambing
| Parametro | EP910LC44-40 | EP910LC-40 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Product Terms (Total) | 240 | — |
| I/O Pins | 24 (bidirectional) | — |
| Dedicated Inputs | 12 | 4 |
| Total Inputs | 36 | — |
| Global Clock Inputs | 2 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (single supply) |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Logic Compatibility | TTL-compatible I/O | — |
| Packhaging | 44-pin PLCC (Plastic Leaded Chip Carrier) | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Programming Method | JEDEC file via LP6/MP9 or compatible programmer | Altera Logic Programmer (PLAD-J), 4-wire serial |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Not applicable (legacy) |
| Manufacturer | — | Rochester Electronics (Altera original) |
| Device Family | — | Altera Classic EPLD - EP910 |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Logic Array Blocks | — | 2 (12 macrocells each) |
| Maximum Toggle Frequency (fMAX) | — | 25 MHz |
| User I/O Pins | — | 36 |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| Lead-Free Status | — | Not applicable |