EP910LC44 vs EP910LC-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC44 sa pamamagitan ng Altera at EP910LC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC44 EP910LC-30
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Product Family Classic EPLD (EP910 Series) —
Manufacturer Altera Corporation (now Intel PSG) —
Device Type Erasable Programmable Logic Device (EPLD) EPLD (Erasable Programmable Logic Device)
Macrocells 24 —
Total Product Terms 240 —
Dedicated Inputs 12 —
I/O Pins 24 —
Total Input Pins 36 (12 dedicated + 24 I/O as inputs) —
Global Clock Inputs 2 —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (nominal, TTL)
Propagation Delay (LC grade) [DATA_NEEDED: propagation delay for LC suffix - exact tPD not in verified data] —
Propagation Delay (LC-30 grade) 33 ns (per EP910LC44-30 verified data) —
Process Technology CMOS CMOS (EPROM-based)
Packhaging 44-pin PLCC (J-leaded) —
Temperature na Operasyon [DATA_NEEDED: commercial 0C-70C or industrial -40C-85C - not in verified data] —
Programming Method EPROM (erasable UV for ceramic; OTP for plastic PLCC) —
Architecture AND-OR sum-of-products with programmable macrocell feedback —
Logic Compatibility TTL-compatible CMOS I/O —
Tindminan RoHS [DATA_NEEDED: not stated in verified data] [DATA_NEEDED: RoHS status]
Macrocell Count — 24
Propagation Delay (tPD) — 30 ns (max)
Maximum Toggle Frequency — 62 MHz
Package Type — PDIP-40 (Plastic DIP, through-hole)
Operating Temperature Grade — Commercial (0C to +70C)
I/O Pin Count — 24
Dedicated Input Pins — 36 (including I/O)
Product Terms per Macrocell — Up to 16
Programming Technology — UV-erasable EPROM cell
Development Tool — Altera MAX+PLUS II
Level ng MSL — [DATA_NEEDED: MSL level]

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