EP910LI-12 vs EP910LI-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-12 sa pamamagitan ng Altera at EP910LI-20T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-12 | EP910LI-20T |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 12 ns | 20 ns |
| Maximum Frequency (fMAX) | 76.9 MHz | 95 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V typical) | 5 V |
| I/O Pins | 24 | 20 |
| Inputs (with input registers) | 36 | — |
| Packhaging | 28-PLCC (windowed ceramic, J-Lead) | CDIP-20 (ceramic DIP, through-hole) |
| Temperature na Operasyon | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Process Technology | 1.0-micron CMOS EPROM | — |
| Power Dissipation (typical) | 200 mW at 5 V | — |
| Programming Method | UV-erasable via windowed package | — |
| Logic Compatibility | TTL-compatible I/O | — |
| Tindminan RoHS | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD (Altera) |
| Logic Array Blocks (LABs) | — | 4 |
| Dedicated Inputs | — | 10 |
| Programming Technology | — | CMOS EPROM (UV-erasable) |
| Programming Voltage | — | 21 V |
| Speed Grade | — | -20 |
| Uri ng Pagpapasok | — | Through-hole |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |