EP910LI-15 vs EP910IPC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-15 sa pamamagitan ng Altera at EP910IPC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-15 | EP910IPC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Product Type | Programmable Logic Device (PLD) | Erasable Programmable Logic Device (EPLD) |
| Device Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Part Number | EP910LI-15 | — |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| Dedicated Inputs | 12 | 12 |
| Input/Output Lines | 24 | — |
| Total User-Signal Resources | 36 | — |
| Speed Grade | 15 ns | — |
| Hanay ng Temperature na Operasyon | -40 °C to +85 °C | — |
| Technology | CMOS | — |
| Packhaging | 44-terminal J-lead ceramic chip carrier (PQCC44) | PDIP-40 (Plastic DIP, 40-pin) |
| Package Pin Count | 44 terminals | — |
| Package Mounting | Surface Mount | — |
| Dielectric/Construction | Ceramic | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: rohs status not confirmed in verified data] |
| REACH Status | unknown | — |
| AEC-Q100 Status | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Conflict Minerals Status | unknown | — |
| Architecture | — | PAL-type, CMOS |
| Macrocells | — | 24 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Propagation Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Temperature na Operasyon | — | 0C to +70C (commercial, IPC suffix) |
| Uri ng Pagpapasok | — | Through-Hole |
| Process Technology | — | CMOS |
| Programming Method | — | JEDEC fuse map via Altera EPLD programmer |
| Bilang ng Pin | — | 40 |