EP910LI-15 vs EP910LI-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-15 sa pamamagitan ng Altera at EP910LI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-15 | EP910LI-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Product Type | Programmable Logic Device (PLD) | — |
| Device Family | Altera Classic EPLD | — |
| Part Number | EP910LI-15 | — |
| Supply Voltage Range | 4.5 V to 5.5 V | — |
| Dedicated Inputs | 12 | 16 |
| Input/Output Lines | 24 | — |
| Total User-Signal Resources | 36 | — |
| Speed Grade | 15 ns | — |
| Hanay ng Temperature na Operasyon | -40 °C to +85 °C | — |
| Technology | CMOS | CMOS, UV-erasable |
| Packhaging | 44-terminal J-lead ceramic chip carrier (PQCC44) | 40-pin Ceramic DIP (Windowed) |
| Package Pin Count | 44 terminals | — |
| Package Mounting | Surface Mount | — |
| Dielectric/Construction | Ceramic | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Status | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Conflict Minerals Status | unknown | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 24 |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| I/O Pins | — | 24 |
| Supply Voltage (VCC) | — | 5 V |
| Temperature na Operasyon | — | -40C to +85C (Industrial) |
| Package Type | — | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | — | Industrial (-40C to +85C) |
| Bilang ng Pin | — | 40 |
| Logic Family | — | EPLD (Erasable PLD) |
| Architecture | — | Sum-of-products macrocell |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |