EP910LI-20T vs EP910LI-30T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-20T sa pamamagitan ng Altera at EP910LI-30T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-20T | EP910LI-30T |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (Altera) | Altera Classic EPLD |
| Macrocells | 24 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Dedicated Inputs | 10 | 10 |
| I/O Pins | 20 | 24 |
| Propagation Delay (tPD) | 20 ns | 30 ns |
| Maximum Frequency (fMAX) | 95 MHz | [DATA_NEEDED: fMAX] |
| Supply Voltage (VCC) | 5 V | — |
| Programming Technology | CMOS EPROM (UV-erasable) | — |
| Programming Voltage | 21 V | — |
| Packhaging | CDIP-20 (ceramic DIP, through-hole) | PQCC-44 (J-lead) |
| Speed Grade | -20 | — |
| Temperature na Operasyon | -40 C to +85 C (industrial) | -40C to +85C (Industrial) |
| Uri ng Pagpapasok | Through-hole | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Clock-to-Output (tCO) | — | [DATA_NEEDED: tCO] |
| Technology | — | CMOS, UV-erasable |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC] |
| Programming Method | — | EPROM (UV-erasable) via Altera Logic Programmer |
| Lead-Free | — | [DATA_NEEDED: Lead-free] |