EP910LI-30 vs EP910LI-50 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-30 sa pamamagitan ng Rochester Electronics at EP910LI-50 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 Obsolete
Pagsanggunian na paghahambing
| Parametro | EP910LI-30 | EP910LI-50 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Altera Classic EPLD EP910 | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Equivalent Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | 50 ns |
| Supply Voltage (VCC) | 5 V ±5% (4.75 V to 5.25 V) | 5 V +/- 10% |
| Supply Current (ICC) | [DATA_NEEDED: ICC standby/active] | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Process Technology | CMOS EPROM, UV-erasable | — |
| Packhaging | 44-pin PQCC / PLCC-44 (J-lead) | — |
| Uri ng Pagpapasok | Surface Mount (socket recommended for UV erasure) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 22 | [DATA_NEEDED: I/O pin count] |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support | EPROM programmer (UV-erasable window) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not verified in scraped data] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) | — |
| Usable Gates | — | 450 |
| Package Type | — | CERDIP-40 (L) |
| Package Pin Count | — | 40 |
| Technology | — | CMOS, UV-erasable EPROM |
| Logic Blocks | — | Classic AND/OR array architecture |
| Speed Grade Suffix | — | -50 (50 ns tPD) |