EP910LI-35H vs EP910LC-35H Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35H sa pamamagitan ng Intel at EP910LC-35H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35H | EP910LC-35H |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Capacity | 900 usable gates | — |
| Macro Cells | 24 | — |
| Speed Grade (tPD) | 35 ns | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCC) | 5 V (±10%) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM cell | CMOS, UV-erasable EPROM |
| Packhaging | 44-pin PLCC (J-lead) | 40-pin Ceramic DIP (H suffix) |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range grade] |
| Standby Current | [DATA_NEEDED: ICCSB] | — |
| Active Supply Current | [DATA_NEEDED: ICC] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Uri ng Pagpapasok | Surface Mount | Through-hole (Ceramic DIP) |
| Tindminan RoHS | unknown | unknown |
| Lead-Free Option (H suffix) | Yes (H suffix) | — |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 10 |
| Erasure Method | — | UV (quartz window on H package) |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| Kuru-kuryente ng Kapayapaan | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |