EP910LI-35H vs EP910LC-35H 比較
詳細並排比較 EP910LI-35H 由 Intel 與 EP910LC-35H 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-35H | EP910LC-35H |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Altera Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Capacity | 900 usable gates | — |
| Macro Cells | 24 | — |
| Speed Grade (tPD) | 35 ns | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCC) | 5 V (±10%) | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS, UV-erasable EPROM cell | CMOS, UV-erasable EPROM |
| 封裝 | 44-pin PLCC (J-lead) | 40-pin Ceramic DIP (H suffix) |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range grade] |
| Standby Current | [DATA_NEEDED: ICCSB] | — |
| Active Supply Current | [DATA_NEEDED: ICC] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| 安裝類型 | Surface Mount | Through-hole (Ceramic DIP) |
| RoHS 狀態 | unknown | unknown |
| Lead-Free Option (H suffix) | Yes (H suffix) | — |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 10 |
| Erasure Method | — | UV (quartz window on H package) |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| 靜態電流 | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |