EP910LI-35T vs EP910LI-40T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35T sa pamamagitan ng Intel at EP910LI-40T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35T | EP910LI-40T |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | Classic EPLD (EP910) | Classic EPLD |
| Logic Elements | 24 macrocells | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | 40 ns |
| Maximum Toggle Frequency (fMAX) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, EPROM-based | CMOS, UV-erasable EPROM |
| Packhaging | 44-pin PLCC (JEDEC) | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC |
| Temperature na Operasyon | -40C to +85C (industrial, 'I' suffix) | -40C to +85C (Industrial) |
| Uri ng Pagpapasok | Surface Mount / Socket | — |
| Programming Method | EPROM (UV-erasable for windowed versions) | Altera Master Programming Unit (MPU), no JTAG |
| Data Retention | [DATA_NEEDED: data retention years] | — |
| Number of I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Macrocells | — | 24 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Product Terms | — | 240 |
| Volte ng Pagbibigay | — | 5 V (typical) |
| Architecture | — | PAL-type with global bus |