EP910LI-35Y vs EP910LC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35Y sa pamamagitan ng Intel at EP910LC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35Y | EP910LC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | Classic (EP910) |
| Usable Gates | 450 | 450 |
| Macrocells | 24 | 24 |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | [DATA_NEEDED: maximum toggle frequency in MHz] | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Process Option | L (low-power CMOS) | — |
| Temperature Grade | Industrial (-40 °C to +85 °C) | — |
| Packhaging | PLCC-44 (J-lead) | PLCC-44 (J-lead, LC suffix) |
| Uri ng Pagpapasok | Surface Mount | — |
| Lead Finish | Lead-free (Y suffix, RoHS-compliant) | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 36 | — |
| Technology | CMOS EPROM/UV-erasable | CMOS EPROM |
| Tindminan RoHS | Compliant (Y suffix) | Not applicable (legacy product) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Bilang ng Pin | — | 44 |
| Programmable Flip-Flops | — | Yes (per macrocell) |
| Output Enable Control | — | Per macrocell |
| Erasure Method | — | UV (windowed) or OTP (plastic) |