EP910LI-40T vs EP910LI-35T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-40T sa pamamagitan ng Intel at EP910LI-35T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-40T | EP910LI-35T |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Classic EPLD | Classic EPLD (EP910) |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| Technology | CMOS, UV-erasable EPROM | CMOS, EPROM-based |
| Volte ng Pagbibigay | 5 V (typical) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (industrial, 'I' suffix) |
| Architecture | PAL-type with global bus | — |
| Packhaging | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC | 44-pin PLCC (JEDEC) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Programming Method | Altera Master Programming Unit (MPU), no JTAG | EPROM (UV-erasable for windowed versions) |
| Logic Elements | — | 24 macrocells |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Uri ng Pagpapasok | — | Surface Mount / Socket |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Number of I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |