EP910PC-20 vs EP910PI-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-20 sa pamamagitan ng Altera at EP910PI-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-20 | EP910PI-40 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Usable Gates | 900 | — |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Packhaging | PDIP-24 (PC suffix) | PDIP-40 (Plastic DIP, 40-pin) |
| Bilang ng Pin | 24 | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | EPROM programmer, JEDEC fuse map | UV-erase + Altera programmer (legacy) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Device Family | — | Classic EPLD |
| Part Number | — | EP910PI-40 |
| Architecture | — | PAL-type macrocell, CMOS, UV-erasable |
| Number of Macrocells | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Lines | — | 24 |
| External Clock Inputs | — | 2 |
| Maksimum na Taktiko ng Oras | — | 25 MHz |
| Propagation Delay (tPD) | — | 43 ns |
| Speed Grade | — | -40 (43 ns) |
| Process Technology | — | CMOS (UV-erasable) |
| Programmable Polarity | — | Yes (user-configurable output) |
| Output Enable Control | — | Yes (per-pin three-state) |