EP910PC-25 vs EP910IPC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-25 sa pamamagitan ng Altera at EP910IPC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-25 | EP910IPC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | 450 |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | 24 |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V |
| Technology | CMOS EPROM | — |
| Packhaging | PDIP-24 (Plastic DIP) | 40-pin PDIP (PDIP-40) |
| Bilang ng Pin | 24 | — |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial grade) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Classic EPLD (EP910 series) |
| Manufacturer | — | Altera (now Intel) |
| Architecture | — | PAL-type EPLD, CMOS, UV/OTP |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Uri ng Pagpapasok | — | Through-Hole |
| Programming Method | — | EPROM cell (OTP / UV erasable) |
| Development Tool | — | MAX+PLUS II |