EP910PC-30T vs EP910PI-30T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-30T sa pamamagitan ng Intel at EP910PI-30T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-30T | EP910PI-30T |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Usable Gates | 900 | 480 |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | — |
| Propagation Delay (tPD) | 30 ns | 30 ns |
| Maximum Clock Frequency (fCNT) | 33.3 MHz | — |
| Process Technology | CMOS | — |
| Volte ng Pagbibigay | 5 V (TTL compatible) | — |
| Packhaging | PDIP-40 (Plastic DIP) | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Temperature na Operasyon | 0C to +70C (commercial) | -40 C to +85 C (industrial) |
| Logic Compatibility | 100% TTL emulation | — |
| Programming | MAX+PLUS II / UV-erasable | Altera Classic device programmer / MAX+PLUS II flow |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS, UV-erasable (windowed ceramic) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |