EP910PI-12T vs EP910PI-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-12T sa pamamagitan ng Altera at EP910PI-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-12T | EP910PI-20T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 2 | — |
| Outputs | 24 | — |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | — |
| Packhaging | 40-pin PDIP (Plastic DIP) | PDIP-40 (PI) |
| Process Technology | CMOS | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programmable Technology | UV-erasable EPROM | — |
| Programming Interface | JEDEC-standard | — |
| Tindminan RoHS | Non-compliant (legacy PDIP package, contains lead) | unknown |
| Katayuan ng Lifecycle | NRND / EOL (mature legacy product) | Not Recommended for New Designs (NRND) |
| Device | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tpd) | — | 20 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Pins | — | 20 |
| Bilang ng Pins | — | 40 |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| Technology | — | CMOS EPROM (UV-erasable) |
| Programming | — | Standard EPROM programmer, JEDEC map |