EP910PI-12T vs EP910PI-25T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-12T sa pamamagitan ng Altera at EP910PI-25T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-12T | EP910PI-25T |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD Family |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 76.9 MHz | — |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | 5 V |
| I/O Pins | 24 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 2 | — |
| Outputs | 24 | — |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | — |
| Packhaging | 40-pin PDIP (Plastic DIP) | 40-pin PDIP (600-mil) |
| Process Technology | CMOS | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programmable Technology | UV-erasable EPROM | — |
| Programming Interface | JEDEC-standard | — |
| Tindminan RoHS | Non-compliant (legacy PDIP package, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Katayuan ng Lifecycle | NRND / EOL (mature legacy product) | — |
| Equivalent Gates | — | 900 (SSI/MSI equivalent) |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Propagation Delay (tpd) | — | 25 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming | — | UV-erasable |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Static Power | — | <100 mW (typical CMOS) |