EP910PI-20T vs EP910PI-25T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-20T sa pamamagitan ng Intel at EP910PI-25T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-20T | EP910PI-25T |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD Family |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | 25 ns |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| Bilang ng Pins | 40 | — |
| Packhaging | PDIP-40 (PI) | 40-pin PDIP (600-mil) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole (DIP) |
| Technology | CMOS EPROM (UV-erasable) | CMOS, UV-erasable EPROM |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming | Standard EPROM programmer, JEDEC map | UV-erasable |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| Katayuan ng Lifecycle | Not Recommended for New Designs (NRND) | — |
| Macrocells | — | 24 |
| Equivalent Gates | — | 900 (SSI/MSI equivalent) |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Supply Voltage (VCC) | — | 5 V |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Static Power | — | <100 mW (typical CMOS) |