EP910PI-25 vs EP910PI-15T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-25 sa pamamagitan ng Intel at EP910PI-15T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-25 | EP910PI-15T |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Device | EP910 | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Process Technology | 5 V CMOS (EPROM-based) | — |
| Packhaging | PDIP-40 (Plastic DIP) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Bilang ng Pin | 40 | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: industrial/commercial temp range] |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| Tindminan RoHS | Non-compliant (PDIP package) | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Volte ng Pagbibigay | — | 4.5 V to 5.5 V (5 V nominal) |
| Propagation Delay (tPD) | — | 15 ns max (speed grade -15) |
| Technology | — | CMOS EEPROM (electrically erasable) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | — | JEDEC-standard, serial/parallel programmer |