EP910PI-30T vs EP910PI-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-30T sa pamamagitan ng Altera at EP910PI-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-30T | EP910PI-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | — |
| Dedicated Inputs | 10 | 12 |
| Propagation Delay (tPD) | 30 ns | — |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V nominal |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Temperature na Operasyon | -40 C to +85 C (industrial) | 0C to +70C (commercial) |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (PDIP package) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device | — | EP910 |
| I/O Pins | — | 24 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Process Technology | — | 5 V CMOS (EPROM-based) |
| Packhaging | — | PDIP-40 (Plastic DIP) |
| Bilang ng Pin | — | 40 |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |