EPC1213PC8 vs EPC1064LC20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC1213PC8 sa pamamagitan ng Altera at EPC1064LC20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC1213PC8 | EPC1064LC20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Uri ng Memory | OTP Configuration PROM (EEPROM cell) | OTP Configuration PROM (Flash-based, one-time programmable) |
| Laki ng Memory | 212 Kbit | 65 kb (65,536 bits) |
| Interface | Serial (4-wire: nCS, DCLK, DATA, OE) | Serial (Passive Serial / daisy-chain compatible) |
| Configuration Mode Supported | FLEX/APEX FPP / PS serial | — |
| Maksimum na Taktiko ng Oras | 6 MHz | — |
| Volte ng Pagbibigay | 3.0 V to 3.6 V | — |
| Programmability | One-Time Programmable (OTP) | — |
| Programming Standard | IEEE Std 1532 / Jam STAPL | — |
| Standby Current | < 50 µA typical | — |
| Temperature na Operasyon | 0 °C to +70 °C (Commercial) | 0 C to 70 C (Commercial) |
| Packhaging | 8-Pin PDIP (R-PDIP-T8) | — |
| Uri ng Pagpapasok | Through-Hole | — |
| Bilang ng Pin | 8 | — |
| Tindminan RoHS | Compliant (post-lead-free Altera revision) | Non-compliant (Sn/Pb finish) |
| Lead-Free | Yes | No (Sn/Pb terminal finish) |
| JEDEC Package Code | R-PDIP-T8 | — |
| Programmable Type | — | OTP (One-Time Programmable) |
| Access Time | — | 90 ns (approximately 10 MHz) |
| Supply Voltage (Operating) | — | 4.5 V to 5.5 V |
| Supply Voltage (Nominal) | — | 5 V |
| Packhaging / Kaso | — | 20-PLCC (LC) J-lead, 9x9 mm |
| No. of Terminals | — | 20 |
| Terminal Finish | — | Tin/Lead (Sn/Pb) |
| Package Code | — | QCCJ (PLCC-20 J-lead) |
| Package Shape | — | Square |
| Compatible Altera FPGA Families | — | ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Modes Supported | — | Passive Serial (PS) with FPP up to 100 MHz on newer FPGAs |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |