EPC1213PC8 vs EPC1064LC20 比較
詳細並排比較 EPC1213PC8 由 Altera 與 EPC1064LC20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1213PC8 | EPC1064LC20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | Obsolete |
| 記憶體類型 | OTP Configuration PROM (EEPROM cell) | OTP Configuration PROM (Flash-based, one-time programmable) |
| 記憶體容量 | 212 Kbit | 65 kb (65,536 bits) |
| 介面 | Serial (4-wire: nCS, DCLK, DATA, OE) | Serial (Passive Serial / daisy-chain compatible) |
| Configuration Mode Supported | FLEX/APEX FPP / PS serial | — |
| 最大時脈頻率 | 6 MHz | — |
| 供應電壓 | 3.0 V to 3.6 V | — |
| Programmability | One-Time Programmable (OTP) | — |
| Programming Standard | IEEE Std 1532 / Jam STAPL | — |
| Standby Current | < 50 µA typical | — |
| 工作溫度 | 0 °C to +70 °C (Commercial) | 0 C to 70 C (Commercial) |
| 封裝 | 8-Pin PDIP (R-PDIP-T8) | — |
| 安裝類型 | Through-Hole | — |
| 腳位數 | 8 | — |
| RoHS 狀態 | Compliant (post-lead-free Altera revision) | Non-compliant (Sn/Pb finish) |
| Lead-Free | Yes | No (Sn/Pb terminal finish) |
| JEDEC Package Code | R-PDIP-T8 | — |
| Programmable Type | — | OTP (One-Time Programmable) |
| Access Time | — | 90 ns (approximately 10 MHz) |
| Supply Voltage (Operating) | — | 4.5 V to 5.5 V |
| Supply Voltage (Nominal) | — | 5 V |
| 封裝 / 外殼 | — | 20-PLCC (LC) J-lead, 9x9 mm |
| No. of Terminals | — | 20 |
| Terminal Finish | — | Tin/Lead (Sn/Pb) |
| Package Code | — | QCCJ (PLCC-20 J-lead) |
| Package Shape | — | Square |
| Compatible Altera FPGA Families | — | ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Modes Supported | — | Passive Serial (PS) with FPP up to 100 MHz on newer FPGAs |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |