EPC1213PC8 vs EPC1064VPC8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC1213PC8 sa pamamagitan ng Altera at EPC1064VPC8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC1213PC8 EPC1064VPC8
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete Obsolete
Uri ng Memory OTP Configuration PROM (EEPROM cell) OTP Configuration PROM (anti-fuse)
Laki ng Memory 212 Kbit —
Interface Serial (4-wire: nCS, DCLK, DATA, OE) Serial (Altera FPGA configuration)
Configuration Mode Supported FLEX/APEX FPP / PS serial —
Maksimum na Taktiko ng Oras 6 MHz —
Volte ng Pagbibigay 3.0 V to 3.6 V —
Programmability One-Time Programmable (OTP) —
Programming Standard IEEE Std 1532 / Jam STAPL —
Standby Current < 50 µA typical —
Temperature na Operasyon 0 °C to +70 °C (Commercial) [DATA_NEEDED: operating temperature range]
Packhaging 8-Pin PDIP (R-PDIP-T8) 8-Pin PDIP (Through-Hole)
Uri ng Pagpapasok Through-Hole Through-Hole
Bilang ng Pin 8 —
Tindminan RoHS Compliant (post-lead-free Altera revision) Non-compliant (per distributor data)
Lead-Free Yes —
JEDEC Package Code R-PDIP-T8 —
Memory Organization — 64K x 1 (65 kb)
Supply Voltage (VCC) — 3.0 V to 3.6 V
Programmable Type — OTP (One-Time-Programmable)
Package Dimensions — 0.300 inch (7.62 mm) PDIP
Target FPGAs — ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Series — EPC1
Access Time / Clock — [DATA_NEEDED: configuration clock frequency]
Program/Erase Cycles — 1 (OTP)
Level ng MSL — [DATA_NEEDED: MSL level]
Supplier Device Package — 8-PDIP

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