EPC1441PI8N vs EPC144PI8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC1441PI8N sa pamamagitan ng Altera at EPC144PI8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPC1441PI8N EPC1441PI8N - 440Kb OTP Config PROM, 8-PDIP | Altera / Intel

EPC1441PI8N - 440Kb OTP Config PROM, 8-PDIP | Altera / Intel

EPC1441PI8N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPC1441PI8N EPC144PI8
Brand Altera Intel
Kategorya Memory ICs FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili NRND
Uri ng Memory OTP Configuration PROM (poly-fuse) OTP Serial Configuration EPROM (UV-erasable package option available)
Memory Capacity 440,800 bits (440 Kbit) —
Configuration Interface Altera Serial (PS) configuration —
Supply Voltage VCC 5.0 V nominal (4.75 V to 5.25 V) [DATA_NEEDED: VCC operating range]
Active Supply Current ICC [DATA_NEEDED: typical active ICC] —
Standby Supply Current ICCSTBY approximately 50 uA —
Programming Method Off-board PROM programmer (poly-fuse OTP) —
Configuration Time <100 ms typical for FLEX10KA loading —
Temperature na Operasyon -40C to +85C (industrial) -40C to +85C (industrial, 'I' suffix)
Packhaging 8-pin PDIP (Plastic DIP, through-hole) PDIP-8 (300 mil)
Bilang ng Pin 8 8
Uri ng Pagpapasok Through-hole (THT) Through-hole (THT)
Lead-Free / RoHS Non-RoHS (legacy through-hole); check suffix for Pb-free option —
Compatible FPGA Families FLEX10K, FLEX10KA, FLEX6000, APEX20K series —
Family Position Top-of-family (largest density: 440Kb) —
Programming Voltage [DATA_NEEDED: VPP programming voltage] —
Endurance One-time programmable (no reprogram cycles) —
Memory Density — 144 Kbit (144,096 bits)
Interface — 4-wire serial (DCLK, DATA, nCS, nINIT_STATUS)
Configuration Clock (max) — [DATA_NEEDED: DCLK maximum frequency]
Process Technology — CMOS EPROM (1.8 V core option per suffix '8')
Programmability — One-Time Programmable (OTP) per bitstream; UV-erasable window package variant also exists
Target FPGA Compatibility — Altera FLEX 6000, FLEX 8000, FLEX 10K, APEX 20K (legacy)
Tindminan RoHS — [DATA_NEEDED: RoHS compliance]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — Not applicable (through-hole)
nINIT_STATUS Output — Open-drain, active-low (per datasheet family convention)
Power-On Reset — Internal automatic (per datasheet family convention)

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