EPC144L20 vs EPC1441LI20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC144L20 sa pamamagitan ng Altera at EPC1441LI20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC144L20 | EPC1441LI20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Uri ng Memory | OTP (One-Time Programmable) Configuration PROM | OTP Configuration PROM (PROM) |
| Memory Density | 440,800 bits | — |
| Organisasyon | 440,800 words × 1 bit (serial) | — |
| Interface | Altera serial configuration (4-pin: nCS, DCLK, DATA, nCONFIG) | — |
| Volte ng Pagbibigay | 3.3 V | 3.3 V |
| Package Type | 20-pin LCC (Leadless Chip Carrier) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40 C to +85 C (industrial) |
| Programming Method | OTP anti-fuse (single program cycle) | One-Time-Programmable via Altera programming hardware |
| Compatible FPGA Families | FLEX 10K, ACEX 1K, APEX 20K, Mercury (legacy Altera) | — |
| Uri ng Pagpapasok | Surface Mount / Socket | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Configuration Clock | [DATA_NEEDED: max DCLK frequency] | — |
| Programming Voltage | [DATA_NEEDED: VPP] | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Configuration Interface | — | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Supported FPGA Families | — | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Packhaging | — | 20-pin PLCC (J-lead, 9x9 mm) |
| Pin Pitch | — | 1.27 mm |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |