EPC16QC100T vs EPC16QC100N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC16QC100T sa pamamagitan ng Altera at EPC16QC100N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC16QC100T EPC16QC100N
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle NRND Obsolete
Uri ng Memory In-System Programmable Configuration PROM —
Laki ng Memory 16 Mbit 16 Mbit (16,777,216 bits)
Interface Serial FPGA configuration + JTAG (IEEE 1149.1) —
Supply Voltage (VCC) 3.3 V 3.0 V to 3.6 V
Programmability In-System Programmable via JTAG —
Daisy-Chain Support Yes (multi-device cascade) —
Data Compression Built-in decompression engine (up to 35% expansion) —
FPGA Compatibility Altera Cyclone, Stratix, ACEX, APEX series —
Packhaging PQFP-100 (20 x 14 mm) 100-pin PQFP (20 x 14 mm)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon 0C to +70C (commercial) 0 C to 70 C
Lead-Free / RoHS Depends on date code; verify per lot —
Level ng MSL 3 (per JEDEC J-STD-020) —
Programming Cycles 100 typical (per Altera datasheet) —
Packaging Suffix 'T' indicates Tape and Reel —
Max DCLK Frequency [DATA_NEEDED: max DCLK frequency] —
Access Time [DATA_NEEDED: serial access time] 90 ns typical
Programmable Type — In System Programmable
Configuration Clock Frequency — 33 MHz max
On-Chip Decompression — Yes (supports compressed bitstreams)
Flash Read Bandwidth — 160 Mbps (16-bit DQ at 10 MHz)
Configuration Interface — FPP / PS / AS via dedicated FPGA pins
JTAG (IEEE 1149.1) ISP — Supported
Lead Free — Yes (per datasheet)
Packaging — Tray
Supported FPGA Families — ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX

Mga Datasheets at Resources

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